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Memory Configuration
3
Like all members of the DSP56300 core family, the DSP56311 addresses three sets of
16 M × 24-bit memory internally : program, X data, and Y data. Each of these memory spaces
includes both internal and external memory (accessed through the external memory interface).
The DSP56311 is extremely flexible because it has several modes to allocate internal memory
between the program memory and the two data memory spaces. You can also configure it to
operate in a special sixteen-bit compatibility mode that allows the chip to use DSP56000 object
code without any change; this can result in higher performance of existing code for applications
that do not require a larger address space. This section provides detailed information on each of
these memory spaces.
3.1 Program Memory Space
Program memory space consists of the following:
Internal program RAM (32 K by default, up to 96 K)
Instruction cache (optional, 1 K) formed from program RAM. When enabled, the memory
addresses used by the internal cache memory are switched to external memory. The
internal memory in this address range switches to cache-only mode and is not available via
direct addressing when cache is enabled. In systems using Instruction Cache, always
enable the cache (CE = 1) before loading code into internal program memory; this
prevents the condition in which code loaded into program memory before cache is enabled
“disappears” after cache is enabled.
Off-chip memory expansion (optional, as much as 64 K in 16-bit mode or 256 K in 24-bit
mode using the 18 external address lines or 4 M using the external address lines and the
four address attribute lines). Refer to the DSP56300 Family Manual , especially Chapter
9 , External Memory Interface (Port A) , for details on using the external memory interface
to access external program memory.
Bootstrap program ROM (192 × 24-bit)
Note:
Program memory space at locations $FF00C0–$FFFFFF is reserved and should not be
accessed.
DSP56311 User’s Manual, Rev. 2
Freescale Semiconductor
3-1
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